Sparse Attention Acceleration with In-Memory Pruning
ReRAM-based sparse attention accelerator that reduces off-chip data movement and recomputes on chip.
This project accelerates sparse attention with a lightweight low-precision thresholding technique mapped to in-memory computing. The architecture targets BERT, ALBERT, GPT-2, and ViT models.
The proposed approach reduces data movement by 94% with only 0.34% accuracy degradation, supported by on-chip recomputation. This work appears in MICRO 2022.